CEVA's New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs
Poster: SySAdmin
Posted on September 7, 2010 at 6:07:01 AM
CEVA's New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs
CEVA-X1643(TM) builds on highly successful CEVA-X architecture; Incorporates native cached memory system, innovative power scaling unit and configurable ARM AXI bus interface
MOUNTAIN VIEW, Calif., Sept. 7 -- CEVA, Inc. [(NASDAQ:CEVA); ], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the CEVA-X1643(TM), a highly-energy efficient, 1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 is the latest family member of the widely used CEVA-X DSP architecture, which has been licensed by more than 25 customers and shipped in over 100 million devices to date.
(Logo: http://photos.prnewswire.com/prnh/20051010/CEVALOGO)
(Logo: http://www.newscom.com/cgi-bin/prnh/20051010/CEVALOGO)
The CEVA-X1643 leverages the architectural efficiency and mature software development environment of the existing CEVA-X family of DSP cores and boasts a number of major enhancements, including;
-- Support for an advanced data cache and tightly coupled memory
architecture, which streamlines software integration and software
porting from other DSP platforms and reduces overall time to market
-- Memory management support simplifying RTOS and multi-tasking
-- Integrated Power Scaling Unit (PSU) enabling a highly energy-efficient
architecture
-- Configurable 64/128 bit AXI system busses supporting high memory
bandwidth
-- Inherent support for seamless migration from TI C6x C-code
-- Over 1 GHz DSP performance using standard 40nm process technology at
worst-case conditions
-- Fully compatible with all CEVA-X family of products
"The CEVA-X1643 is an impressive addition to the CEVA family of DSP cores, offering 1 GHz DSP performance and excellent energy efficiency," said Will Strauss, founder and president of Forward Concepts. "The addition of the data cache memory architecture and power scaling unit to the CEVA-X architecture, while leveraging the CEVA-X industry renowned development tools, should prove appealing to a broad range of semiconductor companies looking for a high-performance DSP core that can efficiently support their legacy code with minimal effort."
"Building on our highly successful CEVA-X family of DSPs, the CEVA-X1643 offers a new level of performance to enable vendors using standard DSP-based chips and ASSPs to move to more flexible and cost-effective core-based SoC designs," said Eran Briman, VP of marketing at CEVA. "The DSP's advanced data cache architecture and software development environment dramatically simplifies the migration of legacy code to the CEVA-X architecture, enabling true, all-in-C programming of the CEVA-X1643."
High performance architecture
The CEVA-X1643 DSP features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle. With a well-balanced pipeline, the CEVA-X1643 can run at over 1 GHz in chips implemented at the 40 nm technology node.
Built-in Standard AXI Bus Bridges
The CEVA-X1643 is equipped with a high performance Advanced eXtensible Interface (AXI) based memory sub-system supporting; configurable AXI bus width, parallel read and write transactions, read after write transactions and other advanced capabilities, ensuring target performance is met in a real-life system. The use of de-facto industry standard system buses together with a fully cached CEVA-X processor enables high performance, shorter design cycle and easy integration into the target SoC.
Highly energy efficient
The CEVA-X1643 DSP core includes an innovative Power Scaling Unit (PSU), which provides advanced power management for both dynamic and leakage power. The core supports multiple clock sources and power domains associated with the main functional units, such as the DSP core and the instruction and data caches. The PSU supports multiple operational modes ranging from full operation, debug bypass, memory retention, to complete power shut-off (PSO). Furthermore, the AXI full duplex busses buses offer low-power features, such as the ability to shut down when no data traffic is present. The CEVA-X1643 offers significant energy savings for both battery-operated and stationary devices, a critical factor in an increasingly energy conscious world.
Seamless migration path for TI C6x based designs
The CEVA-X1643 supports easy migration from off-the-shelf DSP chips to incorporating DSP cores into customer SoC designs. The combination of a compiler-friendly 8-way VLIW and SIMD architecture, an advanced data cache architecture and memory management capabilities enables licensees to efficiently migrate legacy code and ensures similar DSP performance levels at a significantly lower price point.
Enriched software tool chain
The CEVA-X1643 DSP core is supported by CEVA-Toolbox, a software development, debug, and optimization environment that enables near-optimal system performance to be achieved using standard C source code. CEVA-Toolbox includes the Application Optimizer tool, which allows application developers to easily develop software purely in C-Level, thereby eliminating time consuming, hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs. As an example, the Application Optimizer was used to implement the AMR-NB (Adaptive Multi Rate-Narrow Band) vocoder on the CEVA-X1643 DSP core and required just 18 MHz when compiled out-of-the-box (for worst-case frames and streams).
CEVA-X1643 Introduction Video on YouTube
Visit http://www.ceva-dsp.com/media/x1643/ to view an introductory video on the CEVA-X1643 DSP core.
Availability
CEVA-X1643 is currently available for licensing. For more information, contact sales@ceva-dsp.com.
About CEVA, Inc.
CEVA is the world's leading licensor of silicon intellectual property (SIP) DSP cores and platform solutions for the mobile handset, portable and consumer electronics markets. CEVA's IP portfolio includes comprehensive technologies for cellular baseband (2G / 3G / 4G), multimedia, HD video and audio, voice over packet (VoP), Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2009, CEVA's IP was shipped in over 330 million devices, powering handsets from 7 out of the top 8 handset OEMs, including Nokia, Samsung, LG, Motorola, Sony Ericsson and ZTE. Today, more than one in every four handsets shipped worldwide is powered by a CEVA DSP core. For more information, visit http://www.ceva-dsp.com
Photo: http://www.newscom.com/cgi-bin/prnh/20051010/CEVALOGO
AP Archive: http://photoarchive.ap.org/
PRN Photo Desk photodesk@prnewswire.com
http://photos.prnewswire.com/prnh/20051010/CEVALOGO
Source: CEVA, Inc.
CONTACT: Richard Kingston of CEVA, Inc., +1-650-417-7976,
richard.kingston@ceva-dsp.com; or Mike Sottak of Wired Island, Ltd.,
+1-408-876-4418, mike@wiredislandpr.com, for CEVA, Inc.
Web Site: http://www.ceva-dsp.com/
CEVA-X1643(TM) builds on highly successful CEVA-X architecture; Incorporates native cached memory system, innovative power scaling unit and configurable ARM AXI bus interface
MOUNTAIN VIEW, Calif., Sept. 7 -- CEVA, Inc. [(NASDAQ:CEVA); ], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the CEVA-X1643(TM), a highly-energy efficient, 1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 is the latest family member of the widely used CEVA-X DSP architecture, which has been licensed by more than 25 customers and shipped in over 100 million devices to date.
(Logo: http://photos.prnewswire.com/prnh/20051010/CEVALOGO)
(Logo: http://www.newscom.com/cgi-bin/prnh/20051010/CEVALOGO)
The CEVA-X1643 leverages the architectural efficiency and mature software development environment of the existing CEVA-X family of DSP cores and boasts a number of major enhancements, including;
-- Support for an advanced data cache and tightly coupled memory
architecture, which streamlines software integration and software
porting from other DSP platforms and reduces overall time to market
-- Memory management support simplifying RTOS and multi-tasking
-- Integrated Power Scaling Unit (PSU) enabling a highly energy-efficient
architecture
-- Configurable 64/128 bit AXI system busses supporting high memory
bandwidth
-- Inherent support for seamless migration from TI C6x C-code
-- Over 1 GHz DSP performance using standard 40nm process technology at
worst-case conditions
-- Fully compatible with all CEVA-X family of products
"The CEVA-X1643 is an impressive addition to the CEVA family of DSP cores, offering 1 GHz DSP performance and excellent energy efficiency," said Will Strauss, founder and president of Forward Concepts. "The addition of the data cache memory architecture and power scaling unit to the CEVA-X architecture, while leveraging the CEVA-X industry renowned development tools, should prove appealing to a broad range of semiconductor companies looking for a high-performance DSP core that can efficiently support their legacy code with minimal effort."
"Building on our highly successful CEVA-X family of DSPs, the CEVA-X1643 offers a new level of performance to enable vendors using standard DSP-based chips and ASSPs to move to more flexible and cost-effective core-based SoC designs," said Eran Briman, VP of marketing at CEVA. "The DSP's advanced data cache architecture and software development environment dramatically simplifies the migration of legacy code to the CEVA-X architecture, enabling true, all-in-C programming of the CEVA-X1643."
High performance architecture
The CEVA-X1643 DSP features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle. With a well-balanced pipeline, the CEVA-X1643 can run at over 1 GHz in chips implemented at the 40 nm technology node.
Built-in Standard AXI Bus Bridges
The CEVA-X1643 is equipped with a high performance Advanced eXtensible Interface (AXI) based memory sub-system supporting; configurable AXI bus width, parallel read and write transactions, read after write transactions and other advanced capabilities, ensuring target performance is met in a real-life system. The use of de-facto industry standard system buses together with a fully cached CEVA-X processor enables high performance, shorter design cycle and easy integration into the target SoC.
Highly energy efficient
The CEVA-X1643 DSP core includes an innovative Power Scaling Unit (PSU), which provides advanced power management for both dynamic and leakage power. The core supports multiple clock sources and power domains associated with the main functional units, such as the DSP core and the instruction and data caches. The PSU supports multiple operational modes ranging from full operation, debug bypass, memory retention, to complete power shut-off (PSO). Furthermore, the AXI full duplex busses buses offer low-power features, such as the ability to shut down when no data traffic is present. The CEVA-X1643 offers significant energy savings for both battery-operated and stationary devices, a critical factor in an increasingly energy conscious world.
Seamless migration path for TI C6x based designs
The CEVA-X1643 supports easy migration from off-the-shelf DSP chips to incorporating DSP cores into customer SoC designs. The combination of a compiler-friendly 8-way VLIW and SIMD architecture, an advanced data cache architecture and memory management capabilities enables licensees to efficiently migrate legacy code and ensures similar DSP performance levels at a significantly lower price point.
Enriched software tool chain
The CEVA-X1643 DSP core is supported by CEVA-Toolbox, a software development, debug, and optimization environment that enables near-optimal system performance to be achieved using standard C source code. CEVA-Toolbox includes the Application Optimizer tool, which allows application developers to easily develop software purely in C-Level, thereby eliminating time consuming, hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs. As an example, the Application Optimizer was used to implement the AMR-NB (Adaptive Multi Rate-Narrow Band) vocoder on the CEVA-X1643 DSP core and required just 18 MHz when compiled out-of-the-box (for worst-case frames and streams).
CEVA-X1643 Introduction Video on YouTube
Visit http://www.ceva-dsp.com/media/x1643/ to view an introductory video on the CEVA-X1643 DSP core.
Availability
CEVA-X1643 is currently available for licensing. For more information, contact sales@ceva-dsp.com.
About CEVA, Inc.
CEVA is the world's leading licensor of silicon intellectual property (SIP) DSP cores and platform solutions for the mobile handset, portable and consumer electronics markets. CEVA's IP portfolio includes comprehensive technologies for cellular baseband (2G / 3G / 4G), multimedia, HD video and audio, voice over packet (VoP), Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2009, CEVA's IP was shipped in over 330 million devices, powering handsets from 7 out of the top 8 handset OEMs, including Nokia, Samsung, LG, Motorola, Sony Ericsson and ZTE. Today, more than one in every four handsets shipped worldwide is powered by a CEVA DSP core. For more information, visit http://www.ceva-dsp.com
Photo: http://www.newscom.com/cgi-bin/prnh/20051010/CEVALOGO
AP Archive: http://photoarchive.ap.org/
PRN Photo Desk photodesk@prnewswire.com
http://photos.prnewswire.com/prnh/20051010/CEVALOGO
Source: CEVA, Inc.
CONTACT: Richard Kingston of CEVA, Inc., +1-650-417-7976,
richard.kingston@ceva-dsp.com; or Mike Sottak of Wired Island, Ltd.,
+1-408-876-4418, mike@wiredislandpr.com, for CEVA, Inc.
Web Site: http://www.ceva-dsp.com/