Hammer details

Author
Subjugation
Posted
June 13, 2002
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1883
Tags Hardware

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A Japenese site has posted some details about the Hammer CPU. It needs to be translated, but here's a translated portion I got from AMDZone.

As for the weak point of Hammer architecture, the UMA (shared storage
architecture) graphic integration tip/chip set of constitution must be difficult to design. Because as for this, is a memory controller on CPU side. As for the graphic core, as for the that much short ???????? it does not need with most operations. However, just the frame buffer becomes problem. When from the frame buffer territory which houses the data which is drawn in the picture, read-out of the data to the DAC of tip/chip set side is late, signal output to display becomes impossible. Because of that, ever since last year, directly the tip/chip set vendor seems that repeats the AMD and conference concerning the design of UMA tip/chip set.

The topic of the story seems to be a new version of Hammer better suited for integrated video. Since I can see no reason why people would use Hammer for the low end systems with video integration initially instead of an Athlon I don't think this is too big of an issue at this point.


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