Page All:
Page 1
MIPI® Alliance Low Latency Interface Extends Design Options While Saving Cost and Board Space
BARCELONA, Spain, Feb. 29, 2012 /PRNewswire/ -- MOBILE WORLD CONGRESS -- MIPI Alliance today announced the Low Latency Interface (LLI) specification for mobile devices, which offers a point-to-point interconnect between the application processor and modem/baseband processor. Using this high bandwidth interconnect enables the baseband processor to access the application processor's dedicated DRAM memory for baseband processor operation, thus eliminating a separate, dedicated DRAM chip. Industry estimates translate the savings to an approximately $2 USD reduction in the total bill of materials for a smartphone. Board space is also saved, enabling mobile device manufacturers to reduce footprint. For more information, go to http://www.mipi.org/LLI
(Logo: http://photos.prnewswire.com/prnh/20101005/MIPILOGO )
"The LLI specification offers a significant advancement in mobile device system architectures," said Joel Huloux, Chairman of the Board of MIPI Alliance. "This specification opens the door to many design options. Our MIPI Alliance members continue to push the envelope of interface technology, benefitting all areas of the mobile ecosystem."
Layered, Transaction-Level Protocol Improves Data Flow
The LLI interface specification targets low-latency cache refill transactions. Targets and initiators on the application processor and the baseband processor exchange transactions without software intervention - thus reducing latency. The specification also defines a best-effort traffic class, allowing access to remote memory-mapped peripherals without decreasing latency-critical traffic performance. Finally, the LLI interface allows for sideband signal transmission between the two chips, improving overall system communication.
The interface layers begin with an industry-standard physical layer. LLI leverages the MIPI Alliance M-PHY(SM)( )physical layer, a high bandwidth, widely-adopted approach used for peripheral inter-chip interconnects in many mobile and consumer applications. Upper LLI stack layers include a PHY adapter, data link layer and transaction layer.
Scalable Solution Extends Product Life, Reduces Design Time
By using a common physical layer, the LLI specification offers a scalable solution accommodating existing and future requirements in mobile devices. Design configurations can leverage multiple transmission modes, enabling mobile device OEMs to customize their products based on customer needs. LLI also helps reduce overall system power by leveraging the M-PHY SLEEP and HIBERNATE power modes.
SoC designers can connect multiple chips in a "daisy chained" configuration, allowing the chips to share a single memory chip. This enables designers to pursue a multi-chip platform approach, where feature sets can be modified by changing companion chips. This design flexibility extends the product life of application and baseband processors and reduces design time for device manufacturers.
Standardized Interface Reduces Pins and Eases Testing
Previous inter-chip interface solutions were proprietary. A widely adopted solution known as Chip2Chip proved the value of a low latency interface. The LLI interface goes a step farther, delivering equivalent latency and throughput with a substantial reduction in pin count and scalability. As the M-PHY offers scales of High Speed Gears, the application can utilize less pins with higher gear implementation to achieve high throughput and low latency.
With discrete application and baseband processors being used in most mobile devices, a standard chip interconnect dramatically eases system-level testing for OEMs. Faster testing and less time working with proprietary solutions shortens design cycles and gets products to market faster.
Specification Benefits from Broad Industry Support
The LLI Working Group was chartered in 2010, after a 2009 Investigation Group proved an industry need for a standardized, low-latency inter-chip interface specification. Companies contributing to the specification include: Agilent Technologies, Inc., Arasan Chip Systems Inc., Arteris Inc., BitifEye Digital Test Solutions, Broadcom Corporation, Intel Corporation, Motorola Mobility, Inc., Renesas Electronics Corporation, Qualcomm Incorporated, Research In Motion, Samsung Electronics, Co., ST-Ericsson, Synopsys, Inc., Texas Instruments Incorporated, and the University of New Hampshire InterOperability Lab (UNH-IOL).
Several companies have expressed support for the Low Latency Interface specification.
"MIPI LLI provides SoC designers a software stack-free means to share a single memory between two chips using a smaller pin count than alternative solutions," said Charlie Janac, president and CEO of Arteris. "Arteris is proud to be a contributor to LLI and looks forward to contributing to its evolution."
"The new Low Latency Interface provides a scalable, low power solution that helps developers realize cost and area savings in products designed for ultra-mobility," said John Koeter, vice president of marketing for IP and systems at Synopsys. "As a longtime member and supporter of the MIPI Alliance, Synopsys continues to offer IP that supports the rapidly evolving mobile market, including an LLI-compliant DesignWare® MIPI M-PHY IP solution with high data rates and low power consumption to enable highly competitive, future-proof designs."
"TI has been a very strong supporter of the MIPI LLI interface from identifying the need for an industry-standard, low-latency interface through chairing the working group that developed the specification," said Brian Carlson, MIPI Alliance board vice-chair and Senior Technology Strategist, Texas Instruments. "TI developed the OMAP(TM) platform as a discrete architecture to create design flexibility through attachment of companion chips including modems, bridges and more with OMAP processors. TI's OMAP 5 smart multicore application processors, paired with partners' companion chips using LLI, are leading the way with optimized system solutions,"
About MIPI Alliance
MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem and are committed to defining and promoting interface specifications for mobile devices. MIPI Specifications establish standards for hardware and software interfaces which drive new technology and enable faster deployment of new features and services. For more information, visit http://www.mipi.org .
MIPI® is a registered mark of MIPI Alliance, Inc.
Media Contact:
Marcia Barnett
214-868-8861
marcia.barnett@mipi.org
SOURCE MIPI Alliance
Photo:http://photos.prnewswire.com/prnh/20101005/MIPILOGO
http://photoarchive.ap.org/
MIPI Alliance
Web Site: http://www.mipi.org
MIPI® Alliance Low Latency Interface Extends Design Options While Saving Cost and Board Space
BARCELONA, Spain, Feb. 29, 2012 /PRNewswire/ -- MOBILE WORLD CONGRESS -- MIPI Alliance today announced the Low Latency Interface (LLI) specification for mobile devices, which offers a point-to-point interconnect between the application processor and modem/baseband processor. Using this high bandwidth interconnect enables the baseband processor to access the application processor's dedicated DRAM memory for baseband processor operation, thus eliminating a separate, dedicated DRAM chip. Industry estimates translate the savings to an approximately $2 USD reduction in the total bill of materials for a smartphone. Board space is also saved, enabling mobile device manufacturers to reduce footprint. For more information, go to http://www.mipi.org/LLI
(Logo: http://photos.prnewswire.com/prnh/20101005/MIPILOGO )
"The LLI specification offers a significant advancement in mobile device system architectures," said Joel Huloux, Chairman of the Board of MIPI Alliance. "This specification opens the door to many design options. Our MIPI Alliance members continue to push the envelope of interface technology, benefitting all areas of the mobile ecosystem."
Layered, Transaction-Level Protocol Improves Data Flow
The LLI interface specification targets low-latency cache refill transactions. Targets and initiators on the application processor and the baseband processor exchange transactions without software intervention - thus reducing latency. The specification also defines a best-effort traffic class, allowing access to remote memory-mapped peripherals without decreasing latency-critical traffic performance. Finally, the LLI interface allows for sideband signal transmission between the two chips, improving overall system communication.
The interface layers begin with an industry-standard physical layer. LLI leverages the MIPI Alliance M-PHY(SM)( )physical layer, a high bandwidth, widely-adopted approach used for peripheral inter-chip interconnects in many mobile and consumer applications. Upper LLI stack layers include a PHY adapter, data link layer and transaction layer.
Scalable Solution Extends Product Life, Reduces Design Time
By using a common physical layer, the LLI specification offers a scalable solution accommodating existing and future requirements in mobile devices. Design configurations can leverage multiple transmission modes, enabling mobile device OEMs to customize their products based on customer needs. LLI also helps reduce overall system power by leveraging the M-PHY SLEEP and HIBERNATE power modes.
SoC designers can connect multiple chips in a "daisy chained" configuration, allowing the chips to share a single memory chip. This enables designers to pursue a multi-chip platform approach, where feature sets can be modified by changing companion chips. This design flexibility extends the product life of application and baseband processors and reduces design time for device manufacturers.
Standardized Interface Reduces Pins and Eases Testing
Previous inter-chip interface solutions were proprietary. A widely adopted solution known as Chip2Chip proved the value of a low latency interface. The LLI interface goes a step farther, delivering equivalent latency and throughput with a substantial reduction in pin count and scalability. As the M-PHY offers scales of High Speed Gears, the application can utilize less pins with higher gear implementation to achieve high throughput and low latency.
With discrete application and baseband processors being used in most mobile devices, a standard chip interconnect dramatically eases system-level testing for OEMs. Faster testing and less time working with proprietary solutions shortens design cycles and gets products to market faster.
Specification Benefits from Broad Industry Support
The LLI Working Group was chartered in 2010, after a 2009 Investigation Group proved an industry need for a standardized, low-latency inter-chip interface specification. Companies contributing to the specification include: Agilent Technologies, Inc., Arasan Chip Systems Inc., Arteris Inc., BitifEye Digital Test Solutions, Broadcom Corporation, Intel Corporation, Motorola Mobility, Inc., Renesas Electronics Corporation, Qualcomm Incorporated, Research In Motion, Samsung Electronics, Co., ST-Ericsson, Synopsys, Inc., Texas Instruments Incorporated, and the University of New Hampshire InterOperability Lab (UNH-IOL).
Several companies have expressed support for the Low Latency Interface specification.
"MIPI LLI provides SoC designers a software stack-free means to share a single memory between two chips using a smaller pin count than alternative solutions," said Charlie Janac, president and CEO of Arteris. "Arteris is proud to be a contributor to LLI and looks forward to contributing to its evolution."
"The new Low Latency Interface provides a scalable, low power solution that helps developers realize cost and area savings in products designed for ultra-mobility," said John Koeter, vice president of marketing for IP and systems at Synopsys. "As a longtime member and supporter of the MIPI Alliance, Synopsys continues to offer IP that supports the rapidly evolving mobile market, including an LLI-compliant DesignWare® MIPI M-PHY IP solution with high data rates and low power consumption to enable highly competitive, future-proof designs."
"TI has been a very strong supporter of the MIPI LLI interface from identifying the need for an industry-standard, low-latency interface through chairing the working group that developed the specification," said Brian Carlson, MIPI Alliance board vice-chair and Senior Technology Strategist, Texas Instruments. "TI developed the OMAP(TM) platform as a discrete architecture to create design flexibility through attachment of companion chips including modems, bridges and more with OMAP processors. TI's OMAP 5 smart multicore application processors, paired with partners' companion chips using LLI, are leading the way with optimized system solutions,"
About MIPI Alliance
MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem and are committed to defining and promoting interface specifications for mobile devices. MIPI Specifications establish standards for hardware and software interfaces which drive new technology and enable faster deployment of new features and services. For more information, visit http://www.mipi.org .
MIPI® is a registered mark of MIPI Alliance, Inc.
Media Contact:
Marcia Barnett
214-868-8861
marcia.barnett@mipi.org
SOURCE MIPI Alliance
Photo:http://photos.prnewswire.com/prnh/20101005/MIPILOGO
http://photoarchive.ap.org/
MIPI Alliance
Web Site: http://www.mipi.org