Cadence C-to-Silicon Compiler Helps Renesas Realize Quick HEVC IP Development
Poster: SySAdmin
Posted on January 14, 2014 at 8:21:01 AM
Cadence C-to-Silicon Compiler Helps Renesas Realize Quick HEVC IP Development
SAN JOSE, Calif., Jan. 14, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation shortened its design and verification time by 70 percent by utilizing Cadence® C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This enabled the company to quickly offer their customers IP supporting this next-generation video codec.
Renesas established its own coding style and reduced code size by almost half with SystemC to create the HEVC IP at a high level of abstraction. This enabled verification times that were six times faster than register-transfer level (RTL). This approach also enabled Renesas to use C-to-Silicon Compiler to explore many algorithmic implementations to generate high-performance RTL while minimizing power consumption and chip area. To eliminate any potential schedule impact from a significant engineering change order (ECO) late in the project, Renesas developed an ECO flow utilizing C-to-Silicon Compiler with Encounter(®) Conformal(®) ECO Designer. This allowed them to use high-level synthesis to quickly apply and verify a patch to stay on schedule.
"The challenge with developing this HEVC/H.265-compliant IP was to incorporate our proprietary new algorithm, which enables high quality and high compression efficiently," said Toyokazu Hori, department manager of Platform Base Technology Development Department, Automotive Information System Business Division at Renesas Electronics Corporation. "Deploying the system-level design approach with C-to-Silicon Compiler for the entire design addressed this challenge and we were able to implement the new algorithm very efficiently, achieving a good time-to-market for our advanced new IP."
For more information on C-to-Silicon Compiler, visit http://www.cadence.com/news/ctosilicon.
For more information on the Renesas HEVC IP, visit http://www.renesas.com/press/news/2013a/news20131029.jsp.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Conformal, Encounter, and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
SOURCE Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com
SAN JOSE, Calif., Jan. 14, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation shortened its design and verification time by 70 percent by utilizing Cadence® C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This enabled the company to quickly offer their customers IP supporting this next-generation video codec.
Renesas established its own coding style and reduced code size by almost half with SystemC to create the HEVC IP at a high level of abstraction. This enabled verification times that were six times faster than register-transfer level (RTL). This approach also enabled Renesas to use C-to-Silicon Compiler to explore many algorithmic implementations to generate high-performance RTL while minimizing power consumption and chip area. To eliminate any potential schedule impact from a significant engineering change order (ECO) late in the project, Renesas developed an ECO flow utilizing C-to-Silicon Compiler with Encounter(®) Conformal(®) ECO Designer. This allowed them to use high-level synthesis to quickly apply and verify a patch to stay on schedule.
"The challenge with developing this HEVC/H.265-compliant IP was to incorporate our proprietary new algorithm, which enables high quality and high compression efficiently," said Toyokazu Hori, department manager of Platform Base Technology Development Department, Automotive Information System Business Division at Renesas Electronics Corporation. "Deploying the system-level design approach with C-to-Silicon Compiler for the entire design addressed this challenge and we were able to implement the new algorithm very efficiently, achieving a good time-to-market for our advanced new IP."
For more information on C-to-Silicon Compiler, visit http://www.cadence.com/news/ctosilicon.
For more information on the Renesas HEVC IP, visit http://www.renesas.com/press/news/2013a/news20131029.jsp.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.
© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Conformal, Encounter, and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com
SOURCE Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
Web Site: http://www.cadence.com