Cadence Launches Xcelium Parallel Simulator, the Industry's First Production-Proven Parallel Simulator
Poster: SySAdmin
Posted on February 28, 2017 at 1:56:01 AM
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<div xmlns="http://www.w3.org/1999/xhtml" xmlns:xn="http://www.xmlnews.org/ns/" class="xn-newslines">
<h1 class="xn-hedline">Cadence Launches Xcelium Parallel Simulator, the Industry's First Production-Proven Parallel Simulator</h1>
<p class="xn-distributor">PR Newswire</p>
<p class="xn-dateline">BANGALORE and SAN JOSE, Calif., February 28, 2017</p>
</div>
<div class="xn-content" xmlns="http://www.w3.org/1999/xhtml" xmlns:xn="http://www.xmlnews.org/ns/">
<p>
<span class="xn-location">BANGALORE</span> and <span class="xn-location">SAN JOSE, Calif.</span>, <span class="xn-chron">February 28, 2017</span> /PRNewswire/ --</p>
<p>
<b>Highlights:</b> </p>
<p>
<b>-</b> <b>Delivers third generation of simulation with multi-core parallel computing as part of the industry-leading Cadence Verification Suite</b>
<br>
<b>-</b> <b>Provides an average 2X improved single-core performance</b>
<br>
<b>-</b> <b>Offers an average multi-core performance speed-up of 3X for RTL design simulation, 5X for gate-level simulation and 10X for DFT simulations running on today's servers</b>
</p>
<p>Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Xcelium™Parallel Simulator, the industry's first production-ready third generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Cadence® Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects. For more information on the Xcelium simulator, please visit <a href="http://www.cadence.com/go/xcelium" rel="nofollow">http://www.cadence.com/go/xcelium</a>.</p>
<p> (Logo: <a href="http://photos.prnewswire.com/prnh/20140102/SF39436LOGO" rel="nofollow">http://photos.prnewswire.com/prnh/20140102/SF39436LOGO</a> )<br>
</p>
<p>"The ability for ARM and our partners to deliver products to customers' expectations is inexorably bound to rapid and rigorous verification," said <span class="xn-person">Hobson Bullman</span>, General Manager, Technology Services Group at ARM. "The Xcelium Parallel Simulator has demonstrated a 4X speed-up for gate-level simulation and 5X for RTL simulation on ARM®-based SoC designs. Based on these results, we expect Xcelium can enhance our ability to deliver the most complex SoCs in a fast and highly reliable way."</p>
<p>"Fast, scalable simulation is key for us to meet the tight development schedules of our complex 28nm FD-SOI SoCs and ASICs for smart driving and industrial IoT," said <span class="xn-person">Francois Oswald</span>, CPU Team Manager at STMicroelectronics. "We measured 8X faster serial-mode DFT performance with the Cadence Xcelium Parallel Simulator, and therefore selected it as the standard simulation solution for our digital and mixed-signal SoC verification teams."</p>
<p>The Xcelium simulator offers the following benefits aimed at accelerating system development:</p>
<p>- Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick and is the only fully-released simulator based on production-proven parallel simulation technology. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.</p>
<p>- Broad applicability: The Xcelium simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.</p>
<p>- Easy to use: The Xcelium simulator's compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.</p>
<p>- Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time includes SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.</p>
<p>"Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market," said Dr. <span class="xn-person">Anirudh Devgan</span>, Senior Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "The Xcelium simulator combined with JasperGold® Apps, the Palladium® Z1 Enterprise Emulation Platform and the Protium™ S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market, enabling engineers to accelerate the pace of innovation."</p>
<p>The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company's System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.</p>
<p>In related news, Cadence also announced the delivery of another Verification Suite engine today, the Protium S1 FPGA-Based Prototyping Platform, which reduces prototyping time by up to 50 percent. For more information on the Protium platform, please visit <a href="http://www.cadence.com/go/protium-s1" rel="nofollow">http://www.cadence.com/go/protium-s1</a>.</p>
<p style="font-weight: bold">About Cadence</p>
<p>Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence's software, hardware and semiconductor IP are used by customers to deliver products to market faster-from semiconductors to printed circuit boards to whole systems. The company's System Design Enablement strategy helps customers develop differentiated products in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of FORTUNE Magazine's 100 Best Companies to Work For. Learn more at <a href="http://www.cadence.com/" rel="nofollow">cadence.com</a>.</p>
<p>
<sub>© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at</sub> <a href="http://www.cadence.com/go/trademarks" rel="nofollow"><sub>http://www.cadence.com/go/trademarks</sub></a> <sub>are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.</sub>
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<p>
<br>
<b>Media Contact:</b>
<br>
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Cadence Design Systems, Inc.</p>
<p>
<span class="xn-person">Madhavi Rao</span>
<br>
Cadence Design Systems (<span class="xn-location">India</span>) Pvt. Ltd.<br>
<a href="mailto:rmadhavi@cadence.com" rel="nofollow">rmadhavi@cadence.com</a>
<br>
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* @tip Set the styling for your email's preheader links. Choose a color that helps them stand out from your text.
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.preheaderContent a:link, .preheaderContent a:visited, /* Yahoo! Mail Override */ .preheaderContent a .yshortcuts /* Yahoo! Mail Override */{
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/**
* @tip Set the styling for your email's main content links. Choose a color that helps them stand out from your text.
*/
.bodyContent a:link, .bodyContent a:visited, /* Yahoo! Mail Override */ .bodyContent a .yshortcuts /* Yahoo! Mail Override */{
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* @tip Set the styling for your email's left column content links. Choose a color that helps them stand out from your text.
*/
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* @tip Set the styling for your email's center column content text. Choose a size and color that is easy to read.
*/
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line-height: 150%;
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text-align: left;
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/**
* @tip Set the styling for your email's center column content links. Choose a color that helps them stand out from your text.
*/
.centerColumnContent a:link, .centerColumnContent a:visited, /* Yahoo! Mail Override */ .centerColumnContent a .yshortcuts /* Yahoo! Mail Override */{
color: #3d98c6;
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/**
* @tip Set the styling for your email's right column content text. Choose a size and color that is easy to read.
*/
.rightColumnContent{
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font-family: Helvetica;
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line-height: 150%;
padding-top: 0;
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padding-left: 20px;
text-align: left;
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/**
* @tip Set the styling for your email's right column content links. Choose a color that helps them stand out from your text.
*/
.rightColumnContent a:link, .rightColumnContent a:visited, /* Yahoo! Mail Override */ .rightColumnContent a .yshortcuts /* Yahoo! Mail Override */{
color: #3d98c6;
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.leftColumnContent img, .rightColumnContent img{
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* @theme footer
*/
#templateFooter{
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/**
* @tip Set the styling for your email's footer text. Choose a size and color that is easy to read.
* @theme footer
*/
.footerContent{
color: #808080;
font-family: Helvetica;
font-size: 10px;
line-height: 150%;
padding-top: 20px;
padding-right: 20px;
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padding-left: 20px;
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.footerContent.social, .footerContent.social h4 {
text-align: center;
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.footerContent.social a {
margin: 0 10px;
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/**
* @tip Set the styling for your email's footer links. Choose a color that helps them stand out from your text.
*/
.footerContent a:link, .footerContent a:visited, /* Yahoo! Mail Override */ .footerContent a .yshortcuts, .footerContent a span /* Yahoo! Mail Override */{
color: #606060;
font-weight: normal;
text-decoration: underline;
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/* /\/\/\/\/\/\/\/\/ MOBILE STYLES /\/\/\/\/\/\/\/\/ */
@media only screen and (max-width: 480px){
/* /\/\/\/\/\/\/ CLIENT-SPECIFIC MOBILE STYLES /\/\/\/\/\/\/ */
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/**
* @tip Make the fourth-level headings larger in size for better readability on small screens.
*/
h4{
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line-height: 100% !important;
}
/* ======== Header Styles ======== */
#templatePreheader{display: none !important;} /* Hide the template preheader to save space */
/**
* @tip Make the main header image fluid for portrait or landscape view adaptability, and set the image's original width as the max-width. If a fluid setting doesn't work, set the image width to half its original size instead.
*/
#headerImage{
height: auto !important;
max-width: 600px !important;
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<h1 class="xn-hedline">Cadence Launches Xcelium Parallel Simulator, the Industry's First Production-Proven Parallel Simulator</h1>
<p class="xn-distributor">PR Newswire</p>
<p class="xn-dateline">BANGALORE and SAN JOSE, Calif., February 28, 2017</p>
</div>
<div class="xn-content" xmlns="http://www.w3.org/1999/xhtml" xmlns:xn="http://www.xmlnews.org/ns/">
<p>
<span class="xn-location">BANGALORE</span> and <span class="xn-location">SAN JOSE, Calif.</span>, <span class="xn-chron">February 28, 2017</span> /PRNewswire/ --</p>
<p>
<b>Highlights:</b> </p>
<p>
<b>-</b> <b>Delivers third generation of simulation with multi-core parallel computing as part of the industry-leading Cadence Verification Suite</b>
<br>
<b>-</b> <b>Provides an average 2X improved single-core performance</b>
<br>
<b>-</b> <b>Offers an average multi-core performance speed-up of 3X for RTL design simulation, 5X for gate-level simulation and 10X for DFT simulations running on today's servers</b>
</p>
<p>Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Xcelium™Parallel Simulator, the industry's first production-ready third generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Cadence® Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects. For more information on the Xcelium simulator, please visit <a href="http://www.cadence.com/go/xcelium" rel="nofollow">http://www.cadence.com/go/xcelium</a>.</p>
<p> (Logo: <a href="http://photos.prnewswire.com/prnh/20140102/SF39436LOGO" rel="nofollow">http://photos.prnewswire.com/prnh/20140102/SF39436LOGO</a> )<br>
</p>
<p>"The ability for ARM and our partners to deliver products to customers' expectations is inexorably bound to rapid and rigorous verification," said <span class="xn-person">Hobson Bullman</span>, General Manager, Technology Services Group at ARM. "The Xcelium Parallel Simulator has demonstrated a 4X speed-up for gate-level simulation and 5X for RTL simulation on ARM®-based SoC designs. Based on these results, we expect Xcelium can enhance our ability to deliver the most complex SoCs in a fast and highly reliable way."</p>
<p>"Fast, scalable simulation is key for us to meet the tight development schedules of our complex 28nm FD-SOI SoCs and ASICs for smart driving and industrial IoT," said <span class="xn-person">Francois Oswald</span>, CPU Team Manager at STMicroelectronics. "We measured 8X faster serial-mode DFT performance with the Cadence Xcelium Parallel Simulator, and therefore selected it as the standard simulation solution for our digital and mixed-signal SoC verification teams."</p>
<p>The Xcelium simulator offers the following benefits aimed at accelerating system development:</p>
<p>- Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick and is the only fully-released simulator based on production-proven parallel simulation technology. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.</p>
<p>- Broad applicability: The Xcelium simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.</p>
<p>- Easy to use: The Xcelium simulator's compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.</p>
<p>- Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time includes SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.</p>
<p>"Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market," said Dr. <span class="xn-person">Anirudh Devgan</span>, Senior Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "The Xcelium simulator combined with JasperGold® Apps, the Palladium® Z1 Enterprise Emulation Platform and the Protium™ S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market, enabling engineers to accelerate the pace of innovation."</p>
<p>The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company's System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.</p>
<p>In related news, Cadence also announced the delivery of another Verification Suite engine today, the Protium S1 FPGA-Based Prototyping Platform, which reduces prototyping time by up to 50 percent. For more information on the Protium platform, please visit <a href="http://www.cadence.com/go/protium-s1" rel="nofollow">http://www.cadence.com/go/protium-s1</a>.</p>
<p style="font-weight: bold">About Cadence</p>
<p>Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence's software, hardware and semiconductor IP are used by customers to deliver products to market faster-from semiconductors to printed circuit boards to whole systems. The company's System Design Enablement strategy helps customers develop differentiated products in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of FORTUNE Magazine's 100 Best Companies to Work For. Learn more at <a href="http://www.cadence.com/" rel="nofollow">cadence.com</a>.</p>
<p>
<sub>© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at</sub> <a href="http://www.cadence.com/go/trademarks" rel="nofollow"><sub>http://www.cadence.com/go/trademarks</sub></a> <sub>are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.</sub>
</p>
<p>
<br>
<b>Media Contact:</b>
<br>
Cadence Newsroom<br>
<a href="mailto:newsroom@cadence.com" rel="nofollow">newsroom@cadence.com</a>
<br>
+1-408-944-7039<br>
Cadence Design Systems, Inc.</p>
<p>
<span class="xn-person">Madhavi Rao</span>
<br>
Cadence Design Systems (<span class="xn-location">India</span>) Pvt. Ltd.<br>
<a href="mailto:rmadhavi@cadence.com" rel="nofollow">rmadhavi@cadence.com</a>
<br>
+91-9880013765<br>
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