Flex Logix EFLX1K eFPGA Cores Enable Array-Efficient Reconfigurable Logic on 40nm to 180nm Nodes
Poster: SySAdmin
Posted on June 19, 2018 at 7:07:01 AM
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sub-header"style="background:#00837E;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="16px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;hyphens:auto;line-height:16px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h4 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:18px;font-weight:400;hyphens:none;line-height:22px;margin:0;margin-bottom:10px;padding:0;text-align:center;text-transform:uppercase;word-break:none;word-wrap:normal">News From Flex Logix Technologies, Inc.</h4><h5 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;hyphens:none;line-height:18px;margin:0;margin-bottom:0;padding:0;text-align:center;word-break:none;word-wrap:normal">Transmitted by PR Newswire for Journalists on <span class="prevent-break" style="display:inline-block">June 19, 2018 07:00 AM EST </span></h5></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row header" style="background:#e5f2f3;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:0;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h1 style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:20px;font-weight:500;line-height:28px;margin:0;margin-bottom:0;padding:0;text-align:left;word-wrap:normal">Flex Logix EFLX1K eFPGA Cores Enable Array-Efficient Reconfigurable Logic on 40nm to 180nm Nodes</h1> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> </th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table> <table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table><p class="sub-headline" style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;line-height:20px;margin:0;margin-bottom:16px;padding:0;text-align:left"><strong>eFPGA Technology Demonstrations at DAC</strong><p><span class="xn-location">MOUNTAIN VIEW, Calif.</span>, <span class="xn-chron">June 19, 2018</span> /PRNewswire/ -- <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75857KJR-2BwWHTdZ5rovXbOFnfGPurj1Asejb5OjV-2BekA-2BwMkLEhlb8a7zqoEQXVgyJfL0nWRmwtUSWhYnndsgLkI-2Bwn6MECm50IH-2B7eEe9RLufNwpnXm8aj3n3b2U4xlUsbfbBpsNXtkn4h41fbyfBNJepnFSGtE-2BJb-2FdUBmQ3DLGoJjmOFjWr-2FiFerH-2BGDS53KjQQVYBLS9FsLUroWsUskU2RjtpjJxkqvwp-2FKdgkFA0jdUDakPl0ptCmKmnTzFgz6WCwSlKznCXhxP-2BOqbIBRQ-3D-3D" rel="nofollow" target="_blank">Flex Logix<b style="FONT-SIZE: small; FONT-FAMILY: Roboto, arial, sans-serif; WHITE-SPACE: normal; WORD-SPACING: 0px; TEXT-TRANSFORM: none; COLOR: rgb(34,34,34); FONT-STYLE: normal; TEXT-ALIGN: left; ORPHANS: 2; WIDOWS: 2; LETTER-SPACING: normal; BACKGROUND-COLOR: rgb(255,255,255); TEXT-INDENT: 0px; font-variant-ligatures: normal; font-variant-caps: normal; -webkit-text-stroke-width: 0px; text-decoration-style: initial; text-decoration-color: initial">®</b> Technologies, Inc</a>. the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced today a new EFLX<b style="FONT-SIZE: small; FONT-FAMILY: Roboto, arial, sans-serif; WHITE-SPACE: normal; WORD-SPACING: 0px; TEXT-TRANSFORM: none; COLOR: rgb(34,34,34); FONT-STYLE: normal; TEXT-ALIGN: left; ORPHANS: 2; WIDOWS: 2; LETTER-SPACING: normal; BACKGROUND-COLOR: rgb(255,255,255); TEXT-INDENT: 0px; font-variant-ligatures: normal; font-variant-caps: normal; -webkit-text-stroke-width: 0px; text-decoration-style: initial; text-decoration-color: initial">®</b> eFPGA core optimized for the needs of customers on 40nm to 180nm nodes.</p>
<p>"Applications on advanced process nodes such as 28nm and 16nm need large arrays from <span class="xn-money">10K</span> to ><span class="xn-money">200K</span> LUTs," said <span class="xn-person">Geoff Tate</span>, CEO and cofounder of Flex Logix. "The EFLX4K Logic and DSP cores are a great fit for these process nodes and they can be implemented in any 40nm to 180nm in only 6-8 months."</p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:510px;width:100%"><img src="https://mma.prnewswire.com/media/394413/Flex_Logix_Technologies_Logo.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left">
<p>At 40nm to 180nm nodes, customers are interested in reconfigurable logic but need smaller arrays and are very sensitive to area.</p>
<p>The EFLX1K Logic and DSP cores use 10-20% less array/LUT because the interconnect network in the cores implement fewer switch levels for less expandability than the EFLX4K. At the same time, they allow arrays of at least 4x4 to be constructed which is sufficient capacity in the 40nm-180nm nodes. </p>
<p>The EFLX1K Logic core has 368 inputs and 368 outputs with 900 LUT4 equivalent logic capacity. The EFLX1K DSP core has the same number of inputs/outputs but replaces some of the LUTs with DSPs: 10 DSP MACs, pipeline in blocks of 5, with 650 LUT4 equivalent logic capacity. </p>
<p>The EFLX1K Logic and DSP cores can be mixed interchangeably in arrays up to at least 4x4 in size. </p>
<p>Learn more about the EFLX1K Logic and DSP cores from our technologists at DAC <span class="xn-chron">Monday June 25 - Wednesday June 27</span> at Flex Logix's booth #2318. Or email us at <a href="mailto:info@flex-logix.com" rel="nofollow">info@flex-logix.com</a></p>
<p>About Flex Logix <br>Flex Logix, founded in <span class="xn-chron">March 2014</span>, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores, architecture and software. eFPGA can accelerate key workloads 10-100x faster than processors, enable chips to adapt to changing algorithms, protocols, etc and to customize mask sets to meet the needs of multiple customers or market segments. Flex Logix has unique, patented technology for implementing eFPGA: XFLX hierarchical interconnect with twice the density of traditional FPGA mesh interconnect, ArrayLinx interconnect enabling arrays of various sizes and features to be constructed in days from silicon proven GDS blocks, and RAMLinx for integrating any kind of RAM the customer needs. Flex Logix's co-founders Cheng Wang and <span class="xn-person">Dejan Markovic</span> were recognized with the prestigious Outstanding Paper Award by ISSCC for their paper on XFLX technology. Flex Logix's other co-founder <span class="xn-person">Geoff Tate</span> was the founding CEO of Rambus, which pioneered the Semiconductor IP business model, taking the company from 4 employees to a <span class="xn-money">$2 Billion</span> market capitalization. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix has secured approximately <span class="xn-money">$13 million</span> of venture backed capital, is headquartered in <span class="xn-location">Mountain View, California</span> and has sales rep offices in <span class="xn-location">China</span>, <span class="xn-location">Europe</span>, <span class="xn-location">Israel</span>, <span class="xn-location">Japan</span>, <span class="xn-location">Taiwan</span>. More information can be obtained at <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75857KJR-2BwWHTdZ5rovXbOFnfGPurj1Asejb5OjV-2BekA-2BwMkLEhlb8a7zqoEQXVgyJfL0nWRmwtUSWhYnndsgLkI-2Bwn6MECm50IH-2B7eEe9RLufNwpnXm8aj3n3b2U4xlUsPegwuVpCmw3DQW5OBLyeOwIQwC3m9-2FQXdXF7ngr-2FMR-2Bam3x9BhzO45c8dD-2BYo2BxNRZgjK41bBOv8p2xeLwV7py6V-2FbQZnNCWouhFcUjHgR98fWwKqnqLQI32RJhHxdiQG8f7DCC2p52qordjG-2FC-2Bg-3D-3D" rel="nofollow" target="_blank">http://www.flex-logix.com</a> or follow on Twitter at @efpga.</p>
<p>MEDIA CONTACTS<br><span class="xn-person">Kelly Karr</span><br>Tanis Communications<br><a href="mailto:kelly.karr@taniscomm.com" rel="nofollow" target="_blank">kelly.karr@taniscomm.com</a><br>+408-718-9350</p>
<p>Copyright 2018. All rights reserved. Flex Logix and EFLX are registered trademarks of Flex Logix, Inc.</p>
<p> </p>
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<p>"Applications on advanced process nodes such as 28nm and 16nm need large arrays from <span class="xn-money">10K</span> to ><span class="xn-money">200K</span> LUTs," said <span class="xn-person">Geoff Tate</span>, CEO and cofounder of Flex Logix. "The EFLX4K Logic and DSP cores are a great fit for these process nodes and they can be implemented in any 40nm to 180nm in only 6-8 months."</p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:510px;width:100%"><img src="https://mma.prnewswire.com/media/394413/Flex_Logix_Technologies_Logo.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left">
<p>At 40nm to 180nm nodes, customers are interested in reconfigurable logic but need smaller arrays and are very sensitive to area.</p>
<p>The EFLX1K Logic and DSP cores use 10-20% less array/LUT because the interconnect network in the cores implement fewer switch levels for less expandability than the EFLX4K. At the same time, they allow arrays of at least 4x4 to be constructed which is sufficient capacity in the 40nm-180nm nodes. </p>
<p>The EFLX1K Logic core has 368 inputs and 368 outputs with 900 LUT4 equivalent logic capacity. The EFLX1K DSP core has the same number of inputs/outputs but replaces some of the LUTs with DSPs: 10 DSP MACs, pipeline in blocks of 5, with 650 LUT4 equivalent logic capacity. </p>
<p>The EFLX1K Logic and DSP cores can be mixed interchangeably in arrays up to at least 4x4 in size. </p>
<p>Learn more about the EFLX1K Logic and DSP cores from our technologists at DAC <span class="xn-chron">Monday June 25 - Wednesday June 27</span> at Flex Logix's booth #2318. Or email us at <a href="mailto:info@flex-logix.com" rel="nofollow">info@flex-logix.com</a></p>
<p>About Flex Logix <br>Flex Logix, founded in <span class="xn-chron">March 2014</span>, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores, architecture and software. eFPGA can accelerate key workloads 10-100x faster than processors, enable chips to adapt to changing algorithms, protocols, etc and to customize mask sets to meet the needs of multiple customers or market segments. Flex Logix has unique, patented technology for implementing eFPGA: XFLX hierarchical interconnect with twice the density of traditional FPGA mesh interconnect, ArrayLinx interconnect enabling arrays of various sizes and features to be constructed in days from silicon proven GDS blocks, and RAMLinx for integrating any kind of RAM the customer needs. Flex Logix's co-founders Cheng Wang and <span class="xn-person">Dejan Markovic</span> were recognized with the prestigious Outstanding Paper Award by ISSCC for their paper on XFLX technology. Flex Logix's other co-founder <span class="xn-person">Geoff Tate</span> was the founding CEO of Rambus, which pioneered the Semiconductor IP business model, taking the company from 4 employees to a <span class="xn-money">$2 Billion</span> market capitalization. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix has secured approximately <span class="xn-money">$13 million</span> of venture backed capital, is headquartered in <span class="xn-location">Mountain View, California</span> and has sales rep offices in <span class="xn-location">China</span>, <span class="xn-location">Europe</span>, <span class="xn-location">Israel</span>, <span class="xn-location">Japan</span>, <span class="xn-location">Taiwan</span>. More information can be obtained at <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75857KJR-2BwWHTdZ5rovXbOFnfGPurj1Asejb5OjV-2BekA-2BwMkLEhlb8a7zqoEQXVgyJfL0nWRmwtUSWhYnndsgLkI-2Bwn6MECm50IH-2B7eEe9RLufNwpnXm8aj3n3b2U4xlUsPegwuVpCmw3DQW5OBLyeOwIQwC3m9-2FQXdXF7ngr-2FMR-2Bam3x9BhzO45c8dD-2BYo2BxNRZgjK41bBOv8p2xeLwV7py6V-2FbQZnNCWouhFcUjHgR98fWwKqnqLQI32RJhHxdiQG8f7DCC2p52qordjG-2FC-2Bg-3D-3D" rel="nofollow" target="_blank">http://www.flex-logix.com</a> or follow on Twitter at @efpga.</p>
<p>MEDIA CONTACTS<br><span class="xn-person">Kelly Karr</span><br>Tanis Communications<br><a href="mailto:kelly.karr@taniscomm.com" rel="nofollow" target="_blank">kelly.karr@taniscomm.com</a><br>+408-718-9350</p>
<p>Copyright 2018. All rights reserved. Flex Logix and EFLX are registered trademarks of Flex Logix, Inc.</p>
<p> </p>
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