Flex Logix Improves Deep Learning Performance By 10X With New EFLX4K AI eFPGA Core
Poster: SySAdmin
Posted on June 25, 2018 at 7:07:01 AM
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style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table><table class="row sub-header"style="background:#00837E;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="16px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;hyphens:auto;line-height:16px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h4 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:18px;font-weight:400;hyphens:none;line-height:22px;margin:0;margin-bottom:10px;padding:0;text-align:center;text-transform:uppercase;word-break:none;word-wrap:normal">News From Flex Logix Technologies, Inc.</h4><h5 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;hyphens:none;line-height:18px;margin:0;margin-bottom:0;padding:0;text-align:center;word-break:none;word-wrap:normal">Transmitted by PR Newswire for Journalists on <span class="prevent-break" style="display:inline-block">June 25, 2018 07:00 AM EST </span></h5></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row header" style="background:#e5f2f3;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:0;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h1 style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:20px;font-weight:500;line-height:28px;margin:0;margin-bottom:0;padding:0;text-align:left;word-wrap:normal">Flex Logix Improves Deep Learning Performance By 10X With New EFLX4K AI eFPGA Core</h1> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> </th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table> <table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table><p class="sub-headline" style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;line-height:20px;margin:0;margin-bottom:16px;padding:0;text-align:left"><strong>Available on Any Process in 6-8 Months: Enables Reconfigurable AI Matrix Multipliers of Any Size</strong><p><span class="xn-location">MOUNTAIN VIEW, Calif.</span>, <span class="xn-chron">June 25, 2018</span> /PRNewswire/ -- <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75cu-2BbgiAwatkVyHTw-2FgmVmMB5Zv6xzV4-2BGZwYwJRuBRjTWSsPl3WLql8N2uRydrzdpZDyEZNuHfT1vYBsQevcJeP0JPoH2HqiNKfd3MTTpMNNL8XmnsWZVlI1tsyNesYOweIqbFNd36schqNrevEuJZj-2BbHZD74o8jCjveEhMY4-2FlwCjXqvXMzbKtFz2QL-2Bfom0TlQqbgvAEChOe-2FXwZCQPJp2eOl3Ks8SJEt8dBihYs6M-2FMd4aqAsyBdqHwXGDmN0J-2FQTlDYjX4O-2FsVB52oQjw-3D-3D" rel="nofollow" target="_blank">Flex Logix<span>®</span> Technologies, Inc</a>., the leading supplier of embedded FPGA (eFPGA) IP, architecture and software, announced today a new member of the EFLXÃ4K eFPGA Core Family: the EFLX4K Artificial Intelligence (AI) eFPGA core. This new core has been specifically designed to enhance the performance of deep learning by 10X and enable more neural network processing per square millimeter. </p>
<p>Many companies are using FPGA to implement AI and more <span id="spanHghlt4332">specifically</span> machine learning, deep learning and neural networks as approaches to achieve AI. The key function needed for AI are matrix multipliers, which consist of arrays of MACs (multiplier accumulators). In existing FPGA and eFPGAs, the MACs are optimized for DSPs with larger multipliers, pre-adders and other logic which are overkill for AI. For AI applications, smaller multipliers such as 16 bits or 8 bits, with the ability to support both modes with accumulators, allow more neural network processing per square millimeter. </p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:510px;width:100%"><img src="https://mma.prnewswire.com/media/394413/Flex_Logix_Technologies_Logo.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left">
<p>"We've had significant customer interest in using eFPGA for AI applications because of the performance advantages it can deliver in these chip design," said <span class="xn-person">Geoff Tate</span>, CEO and co-founder of Flex Logix. "In fact, one of the first customers Flex Logix announced was <span class="xn-org">Harvard</span> who chose our eFPGA for their deep learning design. Not only will they be presenting this chip at Hot Chips next month, but they are already working on a follow-on 16nm AI chip that will make more extensive use of the Flex Logix EFLX eFPGA."</p>
<p>AI customers want more MACs/second and more MACs/square millimeter, but they also want the flexibility of eFPGA to reconfigure designs as AI algorithms are changing rapidly. They require the ability to switch between 8 and 16 bit modes as needed and to implement matrix multipliers of varying sizes to meet their applications' performance and cost constraints.</p>
<p>The EFLX4K AI eFPGA core leverages Flex Logix's patented XFLX⢠interconnect for an area-efficient, reconfigurable AI solution. It uses a new AI-MAC architecture capable of implementing 8-bit MACs or 16-bit MACs reconfigurably (as well as 16x8 and 8x16). A single EFLX4K AI core in 16nm for example will be about 1.2 square millimeters with 441 8-bit MACs running at 1GHz for a throughput of 441 GigaMACs/second at worst case silicon conditions. The EFLX4K AI core can be arrayed up to at least a 7x7, enabling performance of ~22 TeraMacs/second in worst case silicon <span id="spanHghltcc83">conditions</span>. </p>
<p>The EFLX4K AI is footprint compatible with currently available, silicon proven EFLX4K cores to allow architects and designers the ultimate flexibility in RTL reconfigurability.</p>
<p>The EFLX4K AI eFPGA core is fully supported by Flex Logix's existing software flow using the EFLX Compiler.</p>
<p>As with any EFLX core, the EFLX4K AI eFPGA core can be implemented on any process in six to eight months. Flex Logix's unique eFPGA architecture (XFLX high density interconnect & ArrayLinx⢠interconnect for tiling arrays of any size) enables much faster architectural innovation and iteration than traditional FPGA design approaches. A EFLX4K AI eFPGA core is ~1.2x the area of an EFLX4K Logic core (same width, ~1.2x height).</p>
<p>See us at DAC Booth #2318 this week to learn more or contact us at <a href="mailto:info@flex-logix.com" rel="nofollow">info@flex-logix.com</a>.</p>
<p>About Flex Logix <br>Flex Logix, founded in <span class="xn-chron">March 2014</span>, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores, architecture and software. eFPGA can accelerate key workloads 10-100x faster than processors, enable chips to adapt to changing algorithms, protocols, etc and to customize mask sets to meet the needs of multiple customers or market segments. Flex Logix has unique, patented technology for implementing eFPGA: XFLX hierarchical interconnect with twice the density of traditional FPGA mesh interconnect, ArrayLinx interconnect enabling arrays of various sizes and features to be constructed in days from silicon proven GDS blocks, and RAMLinx for integrating any kind of RAM the customer needs. Flex Logix's co-founders Cheng Wang and <span class="xn-person">Dejan Markovic</span> were recognized with the prestigious Outstanding Paper Award by ISSCC for their paper on XFLX technology. Flex Logix's other co-founder <span class="xn-person">Geoff Tate</span> was the founding CEO of Rambus, which pioneered the Semiconductor IP business model, taking the company from 4 employees to a <span class="xn-money">$2 billion</span> market capitalization. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix has secured approximately <span class="xn-money">$13 million</span> of venture backed capital, is headquartered in <span class="xn-location">Mountain View, California</span> and has sales rep offices in <span class="xn-location">China</span>, <span class="xn-location">Europe</span>, <span class="xn-location">Israel</span>, <span class="xn-location">Japan</span>, <span class="xn-location">Taiwan</span>. More information can be obtained at <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75cu-2BbgiAwatkVyHTw-2FgmVmMB5Zv6xzV4-2BGZwYwJRuBRjTWSsPl3WLql8N2uRydrzdpZDyEZNuHfT1vYBsQevcJeP0JPoH2HqiNKfd3MTTpMNNL8XmnsWZVlI1tsyNesYOPf-2FK5fqnyrvlOWTIflg0TnyTVQcVYqMtey9GoVUI-2BIDxAsbVV3jOLcxVsk-2F3PNdNu5JS2vL5HkgVHnASo9t5vAQhn6ZJeA02t-2FdqsVevNcyvFN1GeedcpLOY641iJvIHmA98QrGyyvi8cPHrYNCqwQ-3D-3D" rel="nofollow" target="_blank">http://www.flex-logix.com</a> or follow on Twitter at @efpga.</p>
<p>MEDIA CONTACTS<br><span class="xn-person">Kelly Karr</span><br>Tanis Communications<br><a href="mailto:kelly.karr@taniscomm.com" rel="nofollow" target="_blank">kelly.karr@taniscomm.com</a><br>+408-718-9350<br></p>
<p>Copyright 2018. All rights reserved. Flex Logix and EFLX are registered trademarks of Flex Logix, Inc.</p>
<p> </p>
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<p>Many companies are using FPGA to implement AI and more <span id="spanHghlt4332">specifically</span> machine learning, deep learning and neural networks as approaches to achieve AI. The key function needed for AI are matrix multipliers, which consist of arrays of MACs (multiplier accumulators). In existing FPGA and eFPGAs, the MACs are optimized for DSPs with larger multipliers, pre-adders and other logic which are overkill for AI. For AI applications, smaller multipliers such as 16 bits or 8 bits, with the ability to support both modes with accumulators, allow more neural network processing per square millimeter. </p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:510px;width:100%"><img src="https://mma.prnewswire.com/media/394413/Flex_Logix_Technologies_Logo.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left">
<p>"We've had significant customer interest in using eFPGA for AI applications because of the performance advantages it can deliver in these chip design," said <span class="xn-person">Geoff Tate</span>, CEO and co-founder of Flex Logix. "In fact, one of the first customers Flex Logix announced was <span class="xn-org">Harvard</span> who chose our eFPGA for their deep learning design. Not only will they be presenting this chip at Hot Chips next month, but they are already working on a follow-on 16nm AI chip that will make more extensive use of the Flex Logix EFLX eFPGA."</p>
<p>AI customers want more MACs/second and more MACs/square millimeter, but they also want the flexibility of eFPGA to reconfigure designs as AI algorithms are changing rapidly. They require the ability to switch between 8 and 16 bit modes as needed and to implement matrix multipliers of varying sizes to meet their applications' performance and cost constraints.</p>
<p>The EFLX4K AI eFPGA core leverages Flex Logix's patented XFLX⢠interconnect for an area-efficient, reconfigurable AI solution. It uses a new AI-MAC architecture capable of implementing 8-bit MACs or 16-bit MACs reconfigurably (as well as 16x8 and 8x16). A single EFLX4K AI core in 16nm for example will be about 1.2 square millimeters with 441 8-bit MACs running at 1GHz for a throughput of 441 GigaMACs/second at worst case silicon conditions. The EFLX4K AI core can be arrayed up to at least a 7x7, enabling performance of ~22 TeraMacs/second in worst case silicon <span id="spanHghltcc83">conditions</span>. </p>
<p>The EFLX4K AI is footprint compatible with currently available, silicon proven EFLX4K cores to allow architects and designers the ultimate flexibility in RTL reconfigurability.</p>
<p>The EFLX4K AI eFPGA core is fully supported by Flex Logix's existing software flow using the EFLX Compiler.</p>
<p>As with any EFLX core, the EFLX4K AI eFPGA core can be implemented on any process in six to eight months. Flex Logix's unique eFPGA architecture (XFLX high density interconnect & ArrayLinx⢠interconnect for tiling arrays of any size) enables much faster architectural innovation and iteration than traditional FPGA design approaches. A EFLX4K AI eFPGA core is ~1.2x the area of an EFLX4K Logic core (same width, ~1.2x height).</p>
<p>See us at DAC Booth #2318 this week to learn more or contact us at <a href="mailto:info@flex-logix.com" rel="nofollow">info@flex-logix.com</a>.</p>
<p>About Flex Logix <br>Flex Logix, founded in <span class="xn-chron">March 2014</span>, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores, architecture and software. eFPGA can accelerate key workloads 10-100x faster than processors, enable chips to adapt to changing algorithms, protocols, etc and to customize mask sets to meet the needs of multiple customers or market segments. Flex Logix has unique, patented technology for implementing eFPGA: XFLX hierarchical interconnect with twice the density of traditional FPGA mesh interconnect, ArrayLinx interconnect enabling arrays of various sizes and features to be constructed in days from silicon proven GDS blocks, and RAMLinx for integrating any kind of RAM the customer needs. Flex Logix's co-founders Cheng Wang and <span class="xn-person">Dejan Markovic</span> were recognized with the prestigious Outstanding Paper Award by ISSCC for their paper on XFLX technology. Flex Logix's other co-founder <span class="xn-person">Geoff Tate</span> was the founding CEO of Rambus, which pioneered the Semiconductor IP business model, taking the company from 4 employees to a <span class="xn-money">$2 billion</span> market capitalization. The company's technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers' hardware. Flex Logix has secured approximately <span class="xn-money">$13 million</span> of venture backed capital, is headquartered in <span class="xn-location">Mountain View, California</span> and has sales rep offices in <span class="xn-location">China</span>, <span class="xn-location">Europe</span>, <span class="xn-location">Israel</span>, <span class="xn-location">Japan</span>, <span class="xn-location">Taiwan</span>. More information can be obtained at <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj0Co-2Bwt-2Bmo8dBZPQCqHnm6HTut8SU3rqXauecAzzSWZh_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75cu-2BbgiAwatkVyHTw-2FgmVmMB5Zv6xzV4-2BGZwYwJRuBRjTWSsPl3WLql8N2uRydrzdpZDyEZNuHfT1vYBsQevcJeP0JPoH2HqiNKfd3MTTpMNNL8XmnsWZVlI1tsyNesYOPf-2FK5fqnyrvlOWTIflg0TnyTVQcVYqMtey9GoVUI-2BIDxAsbVV3jOLcxVsk-2F3PNdNu5JS2vL5HkgVHnASo9t5vAQhn6ZJeA02t-2FdqsVevNcyvFN1GeedcpLOY641iJvIHmA98QrGyyvi8cPHrYNCqwQ-3D-3D" rel="nofollow" target="_blank">http://www.flex-logix.com</a> or follow on Twitter at @efpga.</p>
<p>MEDIA CONTACTS<br><span class="xn-person">Kelly Karr</span><br>Tanis Communications<br><a href="mailto:kelly.karr@taniscomm.com" rel="nofollow" target="_blank">kelly.karr@taniscomm.com</a><br>+408-718-9350<br></p>
<p>Copyright 2018. All rights reserved. Flex Logix and EFLX are registered trademarks of Flex Logix, Inc.</p>
<p> </p>
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